A parallel implementation on modern hardware for geo electrical tomographical software

Hà N Ộ I – 2010 Đ Ạ I H Ọ C Qu Ố C Gia Hà N Ộ I Tr Ườ Ng Đ Ạ I H Ọ C Công Ngh Ệ Nguy Ễ N Hoàng Vũ‌ A Parallel Implementation On Modern Hardware For Geo­‌ Electrical Tomographical Software Khoá Lu Ậ N T Ố T Nghi Ệ P Đ Ạ I H Ọ C H Ệ Chính Quy Ngành: ...

Instruction­Level Parallel (Fined­Grained Control Parallelism) Process­Level Parallel (Coarse­Grained Control Parallelism) Data Parallel (Data Parallelism) These categories are not exclusive of each other. A hardware device (such as the CPU) can belong to all these three groups. 1.1.1 ...

Figure 7 Nvidia GF100 (Fermi) processor with parallel kernel execution Single­precision performance of GF100 is about 1.7 Tflops but double­precision performance is only half at 800 Gflops, significantly better than the Radeon 5870. Previous architectures required that all SMs in the chip worked ...

Smaller tasks. A thread work on the task it meets depth first and steals the task breadth first following the principles: do task from own queue (FIFO) steal task from another queue. This can be applied to one, two or three­dimensional ranges, allowing for effective blocking on data structures ...

CudaHostAlloc which allows host memory to be into CUDA address space providing asynchronous transparent access to data without explicit copy using cudaMemcpy . A notable property that applications using CUDA have is the memory sharing between CUDA memory and OpenGL or DirectX memory. This makes it ...

Equipotential surfaces. If the half space is not homogenous, the value of computed from the above equation is the apparent resistivity. Figure 18 A four electrode arrangement . There are many types of electrode array. [6] provides details about each type of common electrode arrays. A few electrode ...

Β k 1 z T r r T r p k end for. k k z k β k k 1 k 1 1 p k 1 3.2 CPU implementation For each wave number, a large number of linear systems have to be solved. In theory, this equals the number of data points which means that for each electrode arrangement, a linear system must be solved. This is the ...

References‌ [1] Bik A. J. C. Software Vectorization Handbook. Intel Press,2005. [2] Gerber R., Bik A. J. C., Smith K. B., Tian X. Software optimization Cookbook, 2 nd Edition. Intel Press, 2006. [3] FASTRA II, ( http://fastra2.ua.ac.be ) [4] Intel Threading Building Blocks ( ...