Voice Control Circuit Design - 7


- In a typical machine cycle, the ALE signal accumulates twice. The first time allows the 74HC373 to open the low byte address latch port. When ALE drops to 0, the low byte and high byte of the program counter are both present but the EPROM has not been output because PSEN is not active. When the signal rises again, Port 0 already has the Opcode data. The second ALE activation is interpreted similarly and byte 2 is read from the program memory. If the current instruction is a 1-byte instruction, the CPU only reads the Opcode, and the second byte is discarded.

Accessing External Data Memory:

- External data memory is a RAM that can be read or written when enabled by the RD and WR signals. These two signals are located at pins P3.7 (RD) and P3.6 (WR). The MOVX instruction is used to access external data memory and uses a 16-bit data buffer (DPTR), R0 or R1 as an address register.

- RAMs can communicate with the 8951 in the same way as EPROMs except that the RD pin of the 8951 is connected to the OE (Output Enable) pin of the RAM and the WR pin of the 8951 is connected to the WE pin of the RAM. The connection of the address and data buses is similar to that of EPROMs.


D0 – D7 CS RAM A0 A7

Port 0


89C51

EA

ALE

74HC373

OD

G


Address Decoding:

- Address decoding is a necessary requirement to select EPROM, RAM, 8279, ... Address decoding for 8951 to select external memory areas such as microcontrollers. If 8K EPROMs or RAMs are used, the address buses must be decoded to select memory ICs within the 8K limit range: 0000H 1FFFH, 2000H 3FFFH, . .

- Specifically, the 74HC138 decoder IC is used with its outputs connected to the CS (Chip Select) Chip select inputs.

- on EPROM, RAM, etc. memory ICs The following figure allows connecting multiple EPROMs and RAMs.


Address Bus (A0

Data Bus (D0

PSE

74HC138

D0 - D7 OE EPROM A0 A12

8K Bytes CS

CS

CS

RD WR

OE D0 - D7 W

RAM

A0 A12

8K Bytes CS

CS

CS

CBA

E

0

1

2

3

4

5

6

Select other EPROM/RAM

Address Decoding


Overlapping of external data memory areas:

- Since the program memory is ROM, an inconvenient problem arises when developing software for the microcontroller. A common disadvantage of the 8951 is that the external data memory areas overlap each other, because the PSEN signal is used to read the external code memory and the RD signal is used to read the data memory, so a RAM can contain both program and data by connecting the OE line of the RAM to the output of an AND gate with two inputs PSEN and RD. The circuit diagram as shown below allows the RAM to have two functions, both program memory and data memory:



WR RD


PSEN

RAM

WR


OE


Overlapping the External code and data space


-So a program can be loaded into RAM by treating it as data memory and executed by treating it as program memory.

Reset Operation:

- 8951 has a reset input RST that operates at a high level for 2 machine clock cycles, then goes low for the 8951 to start working. RST can be manually activated by a normally open key, the reset circuit diagram is as follows:

+ 5 V

100

Reset


10 F


8.2K ​​


RST


Manual reset.

The state of all the registers in the 8951 after a system reset is summarized as follows:


Register

Content

PC Program Counting

0000H

Accumulator Register A

00H

Register B

00H

PSW register

00H

SP

07H

DPRT

0000H

Port 0 to port 3

FFH

IP

XXX0 0000 B

IE

0X0X 0000 B

The registers are defined.

00H

time

00H

SCON SBUF

00H

PCON (MHOS)

0XXX XXXXH

PCON (CMOS)

0XXX 0000 B

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Voice Control Circuit Design - 7


-The most important register is the program counter register PC which is reset at address 0000H. When the RST input goes low, the program always starts at address 0000H of the program memory. The contents of the on-chip RAM are not changed by the reset input.

IV) Summary of instruction set of vxl 8051 – 8951 – 8952 :

Data Transfer Instructions.



Mnemonic

Instruction code

Hexadecimal

Explanation

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

MOV A, Rn

1 1 1 0 1 n 2 n 1 n 0

E8 EF

(A) (Rn)

MOV A, direct

1 1 1 0 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

E5

Byte 2

(A) (direct)

MOV A, @Ri

1 1 1 0 0 1 1

I

E6 E7

(A) ((Ri))

MOV A, #data

0 1 1 1 0 1 0 0

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

74

Byte 2

(A) #data

MOV Rn, A

1 1 1 1 1 n 2 n 1 n 0

F8 FF

(Rn) (A)

MOV Rn, direct

1 0 1 0 1 n 2 n 1 n 0

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

A8 AF

Byte 2

(Rn) (direct)

MOV Rn, #data

0 1 1 1 1 n 2 n 1 n 0

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

78 7F

Byte 2

(Rn) #data

MOV direct, A

1 1 1 1 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

F5

Byte 2

(direct) (A)

MOV direct, Rn

1 0 0 0 1 n 2 n 1 n 0

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

88 8F

Byte 2

(direct) (Rn)

MOV

direct

direct,

1 0 0 0 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

88 8F

Byte 2

Byte 3

(direct) (direct) (source) (destination)

MOV direct, @Ri

1 0 0 0 0 1 1 I

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

86 87

Byte 2

(direct) ((Ri))

MOV

#data

direct,

0 1 1 1 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

75

Byte 2

Byte 3

(direct) #data

MOV @Ri, A

1 1 1 1 0 1 1

I

F6 F7

((Ri)) (A)

MOV @Ri, direct

1 0 1 0 0 1 1 I

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

A6 A7

Byte 2

((Ri)) (direct)

0 1 1 1 0 1 1 i

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

76 77

Byte 2

((Ri)) (data)

MOV dptr, #data 16

1 0 0 1 0 0 0 0

d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

75

Byte 2

Byte 3

(dptr) #data 15-0 (dpH) #data 15-8 (dpL) #data 7-0

MOVC A, @A +

dptr

1 0 0 1 0 0 1 1

93

(A) ((A) +

(dptr)) External Ram

MOVC A, @A + PC

1 0 0 0 0 0 1 1

83

(A) ((A) + (PC))

External Ram

MOVX A, @Ri

1 1 1 0 0 0 1 i

E2 E3

(A) ((Ri))

External Ram

MOVX A, @ dptr

1 1 1 0 0 0 0 0

93

(A) ((dptr)) External Ram

MOVX @Ri, A

1 1 1 1 0 0 1 i

F2 F3

((Ri)) (A)

MOVX @ dptr, A

1 1 1 1 0 0 0 0

F0

((dptr)) (A)

PUSH direct

1 1 0 0 0 0 0 0

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

C0

Byte 2

(SP) (SP) + 1

((SP)) (direct)

POP direct

1 1 0 1 0 0 0 0

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

D0

Byte 2

(direct) ((SP))

(SP) (SP) – 1

XCH A, Rn

1 1 0 0 1 n 2 n 1 n 0

C8 CF

(direct) (Rn)

XCH A, direct

1 1 0 0 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

C5

Byte 2

(A) (direct)

XCH A, @Ri

1 1 0 0 0 1 1 i

C6 C7

(A) ((Ri))

XCHD A, @Ri

1 1 0 1 0 1 1 i

D6 D7

(A 3-0 ) ((Ri 3-0 ))

MOV @Ri, #data


Mathematical (Arithmetic) Instructions.



Mnemonic

Instruction code

Hexadecimal

Explanation

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

ADD A, Rn

0 0 1 0 1 n 2 n 1 n 0

28 2F

(A) (A) + (Rn)

ADD A, direct

0 0 1 0 0 1 0 1

25

(A) (A) + (direct)

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

Byte 2


ADD A, @Ri

0 0 1 0 0 1 1 I

26 27

(A) (A) + ((Ri))

ADD A, #data

0 0 1 0 0 1 0 0

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

24

Byte 2

(A) (A) + #data

ADDC A, Rn

0 0 1 1 1 n 2 n 1 n 0

38 3F

(A) (A) + (Rn) + (C)

ADDC A, direct

0 0 1 1 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

35

Byte 2

(A) (A) + (direct) + (C)

ADDC A, @Ri

0 0 1 1 0 1 1 I

36 37

(A) (A) + ((Ri)) + (C)

ADDC A, #data

0 0 1 1 0 1 0 0

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

34

Byte 2

(A) (A) + #data +(C)

SUBB A, Rn

1 0 0 1 1 n 2 n 1 n 0

98 9F

(A) (A) - (Rn) - (C)

SUBB A, direct

1 0 0 1 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

95

Byte 2

(A) (A) - (direct) - (C)

SUBB A, @Ri

1 0 0 1 0 1 1 I

96 97

(A) (A) - ((Ri)) - (C)

SUBB A, #data

1 0 0 1 0 1 0 0

d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0

94

Byte 2

(A) (A) - #data -(C)

INC A

0 0 0 0 0 1 0 0

04

(A) (A) + 1

INC Rn

0 0 0 0 1 n 2 n 1 n 0

08 0F

(Rn) (Rn) + 1

INC direct

0 0 0 0 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

05

Byte 2

(direct) (direct) + 1

INC @Ri

0 0 0 0 0 1 1 I

06 07

((Ri)) ((Ri)) + 1

INC dptr

1 0 1 0 0 0 1 1

A3

(dptr) (dptr) + 1

DEC A

0 0 0 1 0 1 0 0

14

(A) (A) - 1

DEC Rn

0 0 0 1 1 n 2 n 1 n 0

18 1F

(Rn) (Rn) - 1

DEC direct

0 0 0 1 0 1 0 1

a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0

15

Byte 2

(direct) (direct) - 1

DEC @Ri

0 0 0 1 0 1 1 I

16 17

((Ri)) ((Ri)) - 1

MUL AB

1 0 1 0 0 1 0 0

A4

(B 15-8 ),(A 7-0 )

(A) (B)


1

0

0

0

0

1

0

0

84

(A 15-8 ),(B 7-0 ) (A)/(B)

DA A

1

1

0

1

0

1

0

0

D4

Contents of A is BCD

DIV AB

Logic Instructions.



Mnemonic

Instruction code

Hexadecimal

Explanation

D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

ANL A, Rn

0

1

0

1

1

n 2 n 1 n 0

58 5F

(A)

(Rn)

(A)

AND

ANL A,

direct

0

a 7

1

a 6

0

a 5

1

a 4

0

a 3

1 0 1

a 2 a 1 a 0

55

Byte 2

(A)

(direct)

(A)

AND

ANL A, @Ri

0

1

0

1

0

1

1

I

5657

(A)

((Ri))

(A)

AND

ANL A,

#data

0

d 7

1

d 6

0

d 5

1

d 4

0

d 3

1 0 0

d 2 d 1 d 0

54

Byte 2

(A)

#data

(A)

AND

ANL direct, A

0

a 7

1

a 6

0

a 5

1

a 4

0

a 3

0 1 0

a 2 a 1 a 0

52

Byte 2

(direct) (direct) and (A)

ANL direct, #data

0

a 7 d 7

1

a 6 d 6

0

a 5 d 5

1

a 4 d 4

0

a 3 d 3

0 1 1

a 2 a 1 a 0 d 2 d 1 d 0

53

Byte 2

Byte 3

(direct) (direct) and #data

ORL A, Rn

0

1

0

0

1

n 2 n 1 n 0

48 4F

(A) (A) OR (Rn)

ORL A,

direct

0

a 7

1

a 6

0

a 5

0

a 4

0

a 3

1 0 1

a 2 a 1 a 0

45

Byte 2

(A)

(direct)

(A)

OR

ORL A, @Ri

0

1

0

0

0

1

1

I

46 47

(A) (A) OR ((Ri))

ORL A,

#data

0

d 7

1

d 6

0

d 5

0

d 4

0

d 3

1 0 0

d 2 d 1 d 0

44

Byte 2

(A) (A) OR #data

ORL direct, A

0

a 7

1

a 6

0

a 5

0

a 4

0

a 3

0 1 0

a 2 a 1 a 0

42

Byte 2

(direct) (direct) OR (A)

ORL direct, #data

0

a 7 d 7

1

a 6 d 6

0

a 5 d 5

0

a 4 d 4

0

a 3 d 3

0 1 1

a 2 a 1 a 0 d 2 d 1 d 0

43

Byte 2

Byte 3

(direct) (direct) OR #data

XRL A, Rn

0

1

1

0

1

n 2 n 1 n 0

68 6F

(A)

(Rn)

(A)

XOR

direct

0

a 7

1

a 6

1

a 5

0

a 4

0

a 3

1 0 1

a 2 a 1 a 0

65

Byte 2

(A)

(direct)

(A)

XOR

XRL A,

@Ri

0

1

1

0

0

1 1 I

66 67

(A)

((Ri))

(A)

XOR

XRL A,

#data

0

d 7

1

d 6

1

d 5

0

d 4

0

d 3

1 0 0

d 2 d 1 d 0

64

Byte 2

(A)

#data

(A)

XOR

XRL direct, A

0

a 7

1

a 6

1

a 5

0

a 4

0

a 3

0 1 0

a 2 a 1 a 0

62

Byte 2

(direct) (direct) XOR (A)

XRL direct, #data

0

a 7 d 7

1

a 6 d 6

1

a 5 d 5

0

a 4 d 4

0

a 3 d 3

0 1 1

a 2 a 1 a 0 d 2 d 1 d 0

63

Byte 2

Byte 3

(direct) (direct) XOR #data

CLR A

1

1

1

0

0

1 0 0

E4

(A) 0

CPL A

1

1

1

1

0

1 0 0

F4

(A) ( A)

RL A

0

0

1

0

0

0 1 1

23

The contents of the accumulator are rotated left by one bit.

RLC A

0

0

1

1

0

0 1 1

33

The contents of the accumulator and carry are rotated left by one bit.

RR A

0

0

0

0

0

0 1 1

03

The contents of the accumulator are rotated right by one bit.

RRC A

0

0

0

1

0

0 1 1

13

The contents of the accumulator and carry are rotated right by one bit.

SWAP A

1

1

0

0

0

1 0 0

C4

(A 3-0 ) (A 7-4 )

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