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Dsp Builder Design Process


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After being processed, the signal will be fed into MLD (maximum likelihood decoder) to determine the original signal. Thanks to that, we will get the original signal.


2.2 Design tools.


2.2.1 DSP Builder software.


The topic is designed using DSP Builder software, a utility designed by Altera to support users to quickly design digital signal processing applications. DSP Builder runs on Matlab's Simulink platform and inherits Simulink's simulation capabilities. Therefore, to use DSP Builder, users need to know about Matlab and Simulink first.

DSP Builder creates a friendly working environment for designing DSP systems. Thanks to the available function blocks, the design becomes easier. Users can create the desired applications and simulate on Simulink to check the results.

DSP Builder provides a tool to convert designs into VHDL format that allows compilation and synthesis into hardware configurations, helping to shorten the time it takes to turn ideas into reality.

DSP Builder is characterized by its bit- and cycle-precision blocks that perform arithmetic and storage functions. They can integrate complex functions by using MegaCore Functions in the DSP Builder model. These Functions enhance the power of DSP Builder and open up a wide range of development possibilities. Error! Reference source not found. presents compilation methods to translate from schematic design to hardware.



Figure 2.10. DSP Builder design process


Matlab Simulink creates a model, using a combination of DSP Builder blocks and Simulink blocks.

RTL (Register Transfer Level) simulation representation: DSP Builder supports simulation for ModelSim software using Tcl scripts. VHDL generated can be used for simulation with other tools.

Use files generated by DSP Builder SignalCompiler block to synthesize RTL. DSP Builder supports Tcl scripts for automatic synthesis using other software programs such as: Quartus II, Synplify, Leonardo Spectrum.


In this thesis, design compilation is performed using Quartus II software version 13.1 and must be on Windows 64 bit platform.

2.2.2 DSP Builder Library.


Figure 2.11. DSP Builder library


Figure 2.11 shows the library groups of DSP Builder. Depending on different versions, DSP Builder will have different libraries. But in general, the library includes the following basic functional blocks:

AltLab Library: This is a library containing design support blocks such as: block for selecting programming component type, block for importing a VHDL or Verilog HDL design into a subsystem, block for returning information: sampling period, maximum number of bits needed during simulation and maximum or minimum value received during simulation. There are two important blocks in the library: SignalCompiler block and SignalTap II Analysis block:



Figure 2.12. Signal Compiler block operation.


The Signal Compiler block is the most important block in DSP Builder. Figure 2.12 shows the interface when running Signal Compiler. This block has the following functions:

Convert Simulink design to RTL VHDL language Generate test files in VHDL or Verilog language

Generate Tcl scripts for Quartus II compilation, or for other software such as: Synplify, Precision RTL, LeonardoSpectrum TM and ModelSim.


Allows creation of SignalTap II (.stp) files


Create files using the Quartus II block format (.bsf)


The SignalTap II Analysis block is used to examine the signals inside the components while the system is running. SignalTap II Analysis can be used for triggers, memory configuration, and waveform display. This project uses this tool to examine each functional block and the data processing of the entire system.

Arithmetic Library: Library of blocks used for arithmetic operations such as comparison, differentiation, integration, multiplication, addition, square root, etc.

Board Library: The board used in the project is the Antenna Board. When we want to connect to any hardware of the board, we just need to add the blocks in the library to the design model.

Complex Type Library: The library provides functions related to complex numbers such as: adding and subtracting complex numbers, calculating amplitude, phase...

Gate and Control Library: This is a library that provides blocks for controlling data paths and logic gates such as multiplexers, demultiplexers, flip flops, AND gates, OR gates, invertors, etc.

IO and Bus Library: This library provides input/output and bus blocks such as: bus conversion (for example, converting from 20-bit bus to 16-bit bus, removing 4 bits), bit separation, source, mass, constants...

Rate Change Library: This library provides blocks to change the speed in the model, mainly used when we want to design a program with more than 1 clock.

The most important block in this library is the PLL block, and this block can only be used when placed at the top level of the model. Also, blocks that use the results of the PLL must be subsystems and not at the same level as the PLL.

Storage Library: The Storage Library provides memory blocks such as ROM, FIFO, LUT (look-up table: storing data in a look-up table)…


MegaCore Functions Library: MegaCore Functions are blocks that perform a complete function on their own, but DSP Builder does not provide these MegaCore Functions out of the box. These MegaCore Functions can be added and are often very complex to control.


2.3 Hardware implementation.


2.3.1 Arria V GT board introduction



Figure 2.13. Antenna Board.


Figure 2.13 is the Altera Arria V GT Development Kit. This kit provides a complete design environment, including all the hardware and software the user needs to develop all FPGA designs and test them in a system environment. The kit is RoHS compliant and includes the following features:

The two FPGAs for the system-level design are the Arria V GT: 504,000 logic elements (LEs), F1517 package, for transfer rates up to 10.3125 Gb/s.

Three input/output slots: 2 high-speed HSMC slots and 1 FMC slot


DDR3 SDRAM with 2Gb memory, QDR II+ with 4.5Mb memory and 1Gb flash memory.

Two SFP+ connections


High speed SMAs and Samtec Bull's Eye connections. Individual power measurements per chip possible.

2.3.2 Components on the Arria V GT board.


2.3.2.1 Antenna Device 5AGTFD7K3F40I3N


On the board there are 2 important devices: FPGA1 and FPGA 2 Arria V GT family with 1517 FineLine BGA pins

504000 logic elements (LEs)


190240 logic response modules (ALMs) M10K memory is 24140 Kb

MLAB memory is 2906 Kb 36 transceivers

16 phase-locked loops (PLLs) 2312 channels 18x18.

Internal voltage 1.15 V


FPGA 1 connects to the following components: Communication ports:

One 8-way PCI Express connection. One USB 2.0 connection

C2C bridge with 29 LVDS inputs, 29 LVDS outputs and 8 transmit and receive channels.

Two SFP+ channels


One 10 Gb/s SMA transmit and receive channel


Three 10 Gb/s Bull's Eye transmit and receive channels Memory:

DDR3 SDRAM 1152 Mb with 72 bit data bus. QDRII + SRAM 72Mb.

Flash synchronized with 16-bit data bus.


Import/export:


LED and LCD:


Eight red and blue 2-color LEDs. Two-line LCD.

Three LEDs indicate configuration selection One LED indicates configuration complete.

Two LEDs indicate HSMC transmit/receive. Three LEDs indicate PCI Express. Five LEDs indicate Ethernet.

Push button:


One push button resets the CPU.


One push button configuration control for MAX II


One push button to load the image into the FPGA from flash memory. One push button to select the image to load from flash memory.

Three push buttons for common use. Eight control switches.

The connection diagram of Arria V GT with the components on the board is as follows:

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